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Alva's Institute of Engineering & Technology

A Unit of Alva's Education Foundation(R), Moodubidire

(Affilliated to VTU, Belgaum, Approved by AICTE, New Delhi, Recognized by Govt. of Karnataka)

AIET Faculty

Mr. Hemanth T S

computer Science and Design

Designation: Assistant Professor
Qualification: B.E. (ECE), M.Tech (VLSI Design and Embedded Systems)
Phone No: 08258- 262724 / 25
Email Id: hemanthts@aiet.org.in
Teaching Experience: 8 Years
Industry Experience: 2025 Years

Educational Details

UG
VLSI Design and Embedded SystemsChannabasaveshwara Institute of Technology, Gubbi, Tumakuru2017-2022
PG-Tech
VLSI Design, ASIC Design, Phase Locked Loops (PLL), Embedded SystemsSiddaganga Institute of Technology, Tumakuru2023-2024

Experience

VLSI Design, ASIC Design, Phase Locked Loops (PLL), Embedded Systems

Basic Electrical, Analog electronic Circuits, VLSI Design, VLSI Process Technology, ASIC Design, System on Chip (SoC) Design, VLSI Testing and Verification, Digital System Design Using Verilog, IOT, Machine Learning

  • Programming Language: C | C++ | Embedded C | Linux/Unix Shell.
  • HDL Language: Verilog | System Verilog | TCl | Perl | Python.
  • EDA Tools: Microsoft Office | Microwind | Keil UVision | MATLAB | Flash Magic | Mentor Graphics | Cadence | Xilinx IDE | Vivado | Libero SoC | SoftConsole.
  • Methodologies: Physical Design | RTL Design | ASIC Design and Verification | Analog Circuit Design | Mixed-Signal IC Design | Static Timing Analysis | DFT | Low Power Design.
  • Protocol: UART | SPI | I2C | USB | CORTEX M3.
  • ML Algorithms: Linear & Logistic Regression | Decision Trees | Random Forest | SVM | KNN | K-Means Clustering.
  • DL Algorithms: ANN | CNN | RNN | LSTM.
  • ML & DL Packages: Scikit-Learn | TensorFlow | Keras | PyTorch (Python, R).
  • Python Numeric Packages: NumPy | SciPy | Pandas | Matplotlib | Seaborn | SymPy | Scikit-Learn
  1. Hemanth T S and Rajeshwari B S, “Predicting Blood Pressure from Photoplethysmogram Data: A Machine Learning Approach” 2024 International Conference on Recent Advances in Science and Engineering Technology (ICRASET).

DOI: 10.1109/ICRASET63057.2024.10895749

  • Actively worked as a volunteer in our branch fest HACKATHONS 2019, organized at CIT, Gubbi, Tumakuru and conducted by CIT-IEEE.
  • “VLSI Design Using Verilog HDL” has participated in an online workshop from Maven Silicon.
  • “Hardware Integration using MATLAB & Simulink” has participated in an online webinar from CoreEL Technologies.
  • “High-Level Synthesis using Vitis HLS” has participated in an online webinar from CoreEL Technologies and AMDXilinx.
  • “Designing with Vivado IP Integrator” has participated in an online webinar from CoreEL Technologies and AMDXilinx.
  • “FPGA Design flow using ZCU104 Board” has participated in an online webinar from CoreEL Technologies and AMDXilinx.
  • “Efficient RTL Generation from C/C++ using AMD Vitis HLS” has participated in an online webinar from CoreEL Technologies and AMD-Xilinx.